The 4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop.
4028 is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. 4028 is a BCD to DECIMAL or BINARY to OCTAL decoder consisting of buffering on all 4 inputs, decoding logic gates, and 10 output buffers.
The 4022 is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit.
The 4011 is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input
The 4006 is comprised of 4 separate "shift register" sections; two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent "single rail" data path. A common clock signal is used for all stages.
Key Features The drive module can directly drive four DC motor, 4WD drive car on the chassis of choice. Drive